1. Field of the Invention
The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device having internal power terminals including a positive power terminal supplying a high potential and a negative power terminal supplying a low potential to the internal device region of a semiconductor chip.
2. Description of the Prior Art
The recent advanced semiconductor microfabrication technique can fabricate high-speed and highly integrated semiconductor chips to make a plurality of chips into a single chip.
It is known that in prior art QFP and PGA packages of such single chip technique, the number of signal terminals is increased due to the single chip so that the number of signal terminals is not sufficient.
It is also known that attention is focusing on flip chip packages in which the number of signal terminals can be large.
The flip chip package can increase the number of signal terminals. It has an intermediate substrate called a buildup substrate connecting a package and a semiconductor chip, which can be provided with a power plane.
The intermediate substrate is provided with the power plane to supply power to an arbitrary location in the semiconductor chip, increasing the power supply ability into the semiconductor chip.
When the power plane of the intermediate substrate supplies power into the semiconductor chip, as shown in the cross-sectional view (FIG. 24) of the A-B broken line of FIG. 23 as an example of a prior art semiconductor chip, the power is supplied in one direction from the top side of the semiconductor chip to an internal device 2810 on a silicon wafer 2850.
Such prior art is disclosed in Japanese Published Unexamined Patent Application No. Hei 06-093062.
In the prior art, however, power is supplied to the internal device arranged between power supply points via the multi-layer internal power wires. When the power wiring impedance for each of the wiring layers is high, a source voltage drop (IR-Drop) occurs.
Accordingly, the present invention has been contrived to realize a structure in which one metal layer of the same layer as an internal power source PAD is provided between the power sources PAD to increase the number of power supply points to an under-layer metal, vertically supplying power from the power supply points.
The semiconductor device described in Japanese Published Unexamined Patent Application No. Hei 06-093062 as another prior art has a tandem electrode structure, as in the present invention. It does not focus on a source voltage drop. The power wiring width is not varied corresponding to internal power consumption. The objects and effects thereof are different from those of the present invention.
Summary of the Invention
A semiconductor device having internal power terminal including a positive power terminal supplying a high potential and a negative power terminal supplying a low potential to the internal device region of a semiconductor chip in which the positive power terminal and the negative power terminal are arranged uniformly in the internal device region of the semiconductor chip and power is supplied from the outside of the semiconductor chip to the internal power terminal, wherein a metalizing metal of the same layer as the internal power terminal is wired between the internal power terminals in a tandem shape so as to be connected to the internal power terminal of the same potential, a top and under layer connection VIA is provided in the position where the tandem metalizing metal wire and an under layer metalizing metal cross so as to supply power to the power wire of the internal device region made of the under layer metalizing metal, and only one metalizing metal layer of the same layer as a power source PAD supplying power from a package of the outside of the semiconductor chip to the internal device region of the semiconductor chip is used to lay the internal power wire between the power sources PAD, thereby supplying power to an internal device.